1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved process of isolating active regions within a semiconductor substrate. The improved isolation process involves etching trenches between active regions, and then by a series of in situ processes, creating a fill dielectric within the trenches.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions. While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends entirely across the field region and laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces Is problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process". Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron MOS technologies. The shallow trench process is better suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, removing away the trench mask layer and any protective layer (such as a nitride layer), and then refilling the shallow trench with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
One problem with the aforedescribed trench process is that the active areas are exposed along the trench walls during the process of removing the trench mask and nitride layer. Removal of the trench mask and nitride may involve a wet etch process that may result in contamination of the active areas along the trench walls. To avoid exposing the sidewalls of the active area, a thin thermally-grown oxide may be created to line the trenches and serve as an etch stop along the active area sidewalls.
A further problem with the "shallow trench process" is that it involves numerous process steps in varying chambers, thereby complicating the overall semiconductor fabrication process. For example, the process may involve transporting wafers from a plasma etch chamber for forming the trenches to a thermal oxidation chamber for growing the thin protective oxide. The wafers are then transported again to an etch chamber for removal of the trench mask and nitride layer. This may be followed by placing the topography into a chemical vapor deposition (CVA) chamber for deposition of the fill dielectric. After the fill dielectric is deposited, the wafers are again moved to a chemical mechanical polish (CMP) chamber or alternatively a plasma etch-back chamber for planarization.
The complexity of the "shallow trench isolation" process may decrease the overall throughput of the semiconductor fabrication process. The time spent transporting wafers between the various chambers may amount to a significant portion of the overall process time. Thus, the "shallow trench isolation" process may be detrimental to fabrication efficiency, thereby increasing fabrication cost. Furthermore, transportation of the wafers between the various process chambers required for the "shallow trench isolation" process may expose the wafers to contaminants both inside and outside the various chambers. Also, the transferal of wafers between the various chambers employed in the above process may result in thermal stress when wafers are removed from a warm chamber to ambient conditions. Also, the risk of physical damage to the wafers increases when the wafers are transported.
While the trench isolation process has many advantages over LOCOS, it still may have detrimental effects on overall process efficiency and may result in wafers being exposed to contaminants and other risks. A need therefore exists in producing a process which can utilize the advantages of shallow trench isolation but with improved efficiency and less exposure to contaminants and other risks outside the reaction chambers. Thus, it is desirable to have a process that is capable of forming isolation trenches between active areas and filling the isolation trenches with a fill dielectric. It is further desirable that the process does not have a detrimental effect on the active area sidewalls. It is also desirable that the process have improved efficiency and less exposure to contaminants and thermal or physical stress outside reaction chambers. Thus, it would be beneficial to employ a "shallow trench isolation" process with reduced cost and cycle time compared to a conventional "shallow trench isolation" process. The desirous process must be cleaner and safer than conventional shallow trench isolation processes.